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6 august 2003 Ottawa, Ontario Lightwave -- Zarlink Semiconductor today unveiled a high-performance analog phase-locked loop (PLL) timing chip for optical line cards operating at up to OC-192 rates. According to the company, the ZL30414 device contains six output clocks more than any competing product and features jitter performance that surpasses industry specifications.
Analog PLLs perform timing and synchronization functions in communications equipment, including SONET/SDH line cards used in network core, metro, edge, and access equipment. Zarlink's flexible ZL30414 analog PLL accepts one clock signal and simultaneously outputs six low-jitter, higher-frequency clocks.
"At OC-192 rates, jitter performance is a leading design parameter," explains Darren Ladouceur, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Our ZL30414 device beats industry jitter specifications, and by providing six output clocks at three different frequencies, delivers cost and footprint improvements."
With the ZL30414 device and the ZL30406 chip introduced in May 2003, Zarlink now offers analog PLLs for SONET/SDH line cards operating at rates from OC-3/STM-1 to OC-192/STM-64. Zarlink also offers reference designs that help customers determine their requirements and implement system-level timing and synchronization solutions.
Improved jitter performance
Ultra-low jitter, measured in picoseconds, is crucial in systems operating at high speeds or frequencies. For systems operating at OC-192 and STM-64 systems operating at 10 Gbits/sec, the jitter budget--the amount of timing variation allowed from various sources--is extremely small, making the performance of timing devices critical.
The jitter performance of the ZL30414 analog PLL easily meets Telcordia and International Telecommunications Union-Telecommunications (ITU-T) requirements for OC-192 and STM-64 systems. The chip's jitter performance is 0.52-p/sec rms, providing significant margin against Telcordia's GR-253-CORE jitter requirement of 1 p/sec rms. The ZL30414 device delivers a maximum peak-to-peak jitter performance of 6.95 p/sec, surpassing ITU-T G.813 Option 1 and 2 requirements for a maximum peak-to-peak jitter performance of 10 p/sec for STM-64 rates.
Direct interface with line card components
The ZL30414 device accepts one input reference clock at 19.44 MHz and provides six output clocks: four differential LVPECL (low voltage positive emitter coupled logic) clocks at 622.08 MHz, the most common frequency for OC-192/STM-64 devices; a differential CML (current mode logic) clock at 155.52 MHz; and a 19.44-MHz CMOS (complementary metal oxide silicon) clock.
The four LVPECL clocks interface directly to such line card devices as framers, mappers, and SERDES (serializer/deserializer) chips. By providing the logic level required by these devices, the ZL30414 analog PLL eliminates the need for glue logic, which is required when using most competing products, say company representatives. Glue logic leads to a more complex design, consumes power, increases design footprint and cost, and adds to the jitter budget.
The ZL30414 device is in volume production. The chip is offered in a 64-pin thin quad flat pack (TQFP) measuring 10 mm x 10 mm. The ZL30414 is priced at $55.84 in quantities of 1,000.
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