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March 24, 2005 Rochester, NY -- From Xelic, a provider of networking and engineering intellectual property and applications, the XCSTPP12 is a SONET/SDH tributary payload processor core for ASIC and FPGA applications that performs tributary pointer processing, aligns outgoing tributaries, and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate.
According to the company, the device implements the industry-standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2, or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
"The XCSTPP12 adds to Xelic's growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level," contends Doug Bush, director of IP development at Xelic.
The company's cores are available under flexible licensing terms and come with full documentation, as well as a comprehensive suite of self-checking tests. Core customization and integration services are also available.
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